FIG. 1 illustrates a block diagram of a conventional signal processing system 10. As illustrated in FIG. 1, an input signal is amplified and transmitted to an analog filter 11, and further converted into a digital signal by an A/D converter 13 after being filtered by the analog filter 11. An output node of the A/D converter 13 is coupled to a signal processing circuit having an automatic-gain-control (AGC) circuit 15, a digital filter 17, a carrier synchronizer 19, an equalizer 21 and an error correction/decoding circuit 23, which are coupled in series with each other. For various A/D converters with sigma-delta A/D converters, the signal-to-noise and distortion ratio (SNDR) performance will significantly degrade when the amplitude of the input signal exceeds a full scale of the ADC's input range and results in signal overloading of the converter. The overloading may further incur various problems to the DSP signal processing system 10. For example, when the A/D converter fails due to the input signal overloading, we can see failure of the equalizer 21 or even collapse of the whole DSP circuit's function, which is coupled to the A/D converter's output 13. When the input signal falls back into the full scale range, the DSP circuit has to re-converge again from an initial state, which would take a long time. From a system performance/function point of view, the long recovery is highly undesirable.
However, it happens in many communication systems that the input signals are occasionally overloaded even during its normal operations. For example, the amplitude of an out-of-band signal or interference signal can exceed that of an in-band signal by 20 to 40 dB (these interferences are usually called blockers in Radio Frequency applications). Moreover, the peak to average ratio (PAR) of the real signal may be too high due to modulation, fading or echo of signals. The resulting pulses may cause collapse of the whole signal processing system's function, and this is one of the reasons why interleaving/de-interleaving technology is required in many communication systems. The overloading of input signal may also be caused by other factors. In brief, the A/D converters used in the communication systems generally have to process input signals with hugely-varying amplitude that often exceeds its maximum input range.
Some circuits have been developed to deal with the overloading problem. For example, in a typical receiving system, an amplifier, a filter and/or mixer (not shown) may be coupled in front of the A/D converter 13 as illustrated in FIG. 1, and digital signal processing circuits may be coupled to the output. To deal with signal amplitude variations, the front-stage amplifier may be an AGC amplifier. The amplitude or power of the input signal can be adjusted by controlling the gain of the AGC amplifier. Accordingly, the amplitude of the input signal may be adjusted to a range that can be properly processed by the A/D converter. However, assuming that the input signal has a PAR value of 20 dB, the SNR needed at the output node of the A/D converter is greater than 30 dB, and the blocker is of 30 dB or higher, then the AGC level can be set to be 50 dB lower than a maximum value of the SNDR of the A/D converter. Thus, it is required to use an A/D converter with a SNDR value higher than 80 dB. However, the circuit schematic of high-performance (SNDR>80 dB) high-frequency (10 MHz or higher) A/D converters are very complicated, if feasible at all. Such high-performance A/D converters are sensitive to parasite effects or to the environment (i.e. the interferences produced by the peripheral circuit components on the same chip), and therefore the high-performance A/D converters may not be integrated within a system on chip (http://www.stanford.edu/˜murmann/adcsurvey.html).
Another conventional solution to the overloading problem is using several A/D converters in parallel in a system. Moreover, a detection circuit is also included to detect the occurrence of overloading. When the overloading is detected, one or more of the A/D converters may be chosen to process the overloaded input signal. In contrast, some other A/D converter(s) may be chosen when no overloading is detected. However, the switching of the A/D converters may disrupt the signal conversion and bring unwanted long latency.
Furthermore, to deal with the impulsive interferences, which often cause overloading of the data converters, interleaver and de-interleaver circuits are defined in the communication channel protocol used in many communication systems to spread out the impulsive noises introduced by the communication channel in time or frequency domains. However, these circuits have to be defined at the communication system level and be implemented in both the transmitter and receiver. The larger the interleaver and de-interleaver are, the more memory space is needed.
For high bandwidth A/D converters with very high SNDR requirements, continuous-time sigma-delta analog-to-digital conversion circuits are becoming more and more important. In wireless communication systems such as the GSM or WCDMA system, the continuous-time sigma-delta A/D conversion circuit has already become a critical component. A typical continuous-time sigma-delta A/D conversion circuit usually includes a continuous-time filter, a quantizer, a feedback DAC and summation circuits.
Feedback digital-to-analog (D/A) converter(s) is used in the sigma-delta A/D converters to feed back a quantized signal output by a quantizer to a summing stage at the most front stage of the sigma-delta A/D converter. The feedback D/A converter usually determines the resolution of the whole sigma-delta A/D converter, especially for the high resolution continuous-time sigma-delta A/D converters. In particular, the linearity of the feedback D/A converters determines the resolution of the whole ADC. Thus, many methods have been developed to improve the linearity of the D/A converters. For example, some use Dynamic Element Matching (DEM) or similar signal processing techniques. The DEM swaps the DAC's unit elements so they are randomly picked to contribute to the output. The DEM or similar techniques move the quantization noise to a higher frequency, which can be subsequently filtered by the loop filter. The linearity of DAC is positively dependent on the number of bits it has, which means that a DAC with higher linearity requires more bits. However, the more bits a DAC has, the more latency the DEM will cause, which limits the maximum operating frequency of the DAC and thus limits the over sampling ratio (OSR) of the delta sigma converter. Thus, there is a trade off between the DAC linearity and the clock frequency at which the DAC operates). Some converters use a switch capacitor return to zero (SCRZ) structure (Timir Nandi, “Continuous-Time ΔΣ Modulators with Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC”, IEEE JSSC Vol. 48, No. 8, August 2013); and some converters use a filter to estimate the error of the feedback D/A converter more accurately (Pascal Witte, “Hardware Complexity of a Correlation Based Background DAC Error Estimation Technique for Σ-Δ ADCs”, 2167-2170, Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on). However, these sigma-delta converters are complicated in structure and sensitive to the parasite effect and interferences from the environment, and thus are difficult for implementation. In the following, we classify DACs into two types: a high linearity type that utilizes various linearization techniques such as DEM or filter, as given above, and a regular type which only relies on intrinsic device matching to achieve its linearity. The high linearity ones are often associated with additional latency introduced by the linearization techniques.
Thus, there is a need for sigma-delta A/D converters capable of processing input signals with hugely-varying amplitude while not requiring an improved linearity of the feedback D/A converters.